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ace24 la 512 a two - wire serial eeprom ver 1.1 1 description the ace24la512a provides 524288 bits of serial electrically erasable and programmable read - only memory (eeprom), organized as 65536 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where ow - power and low - voltage operation are essential. the ace24la512a offers an additional page, named the identification page ( 128 bytes). the identification page can be used to store sensitive application parameters which can be (later) permanently locked in re ad - only mode. features ? compatible with all i2c bidirectional data transfer protocol ? memory array: 512 kbits ( 64 kbytes) of eeprom page size: 128 bytes additional write lockable page ? single supply voltage and high speed: 1 mhz ? random and sequential read mo des ? write: byte write within 3 ms page write within 3 ms partial page writes allowed ? write protect pin for hardware data protection ? schmitt trigger, filtered inputs for noise suppression ? high - reliability endurance: 1 million write cycles data retention: 10 0 years ? enhanced esd/latch - up protection hbm 8000v ? 8 - lead dip/sop/tssop and uson3*2 - 8 packages absolute maximum ratings dc supply voltage - 0.3v to 6.5v input / output voltage gnd - 0.3v to v cc +0.3v operating temperature - 40 to 85 storage temperature - 6 5 to 150 electrostatic pulse (human body model) 8000v n otice : stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any oth er conditio ns above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ace24 la 512 a two - wire serial eeprom ver 1.1 2 packaging type sop - 8 tssop - 8 dip - 8 u son3*2 - 8 pin configurations pin name type functions ao - a2 i address inputs sda i/o serial data scl i serial clock input wp i write protect gnd p ground v cc p power supply ordering informat ion ace24la512a xx + x h pb - free u : tube t : tape and reel fm: sop - 8 tm: tssop - 8 dp: dip - 8 ua8: uson3*2 - 8 halogen - free
ace24 la 512 a two - wire serial eeprom ver 1.1 3 block diagram
ace24 la 512 a two - wire serial eeprom ver 1.1 4 pin descriptions d evice /p age a ddresses (a2, a1 and a0): the a2, a1 and a0 pins are device address inputs that are hard wire for the ace24la 512a . eight 512k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). s erial d ata (sda): the sda pin is bi - directional for serial data transfer. this pin is open - drain driven and ma y be wire - ored with any number of other open - drain or open - collector devices. s erial c lock (scl): the scl input is used to positive edge clock data into each eepro m device and negative edge clock data out of each device. w rite p rotect (wp): the ace24la512 a has a write protect pin that provides hardware data protection. the write protect pin allows normal read/write operations when connected to ground (gnd). when the write protection pin is connected to vcc, the write protection feature is enabled and opera tes as shown in the following table 1 . table 1. write protect wp pin status part of the array protected ace24la512a at v cc full ( 512 k) array at gnd normal read / write operations memory organization ace24la512a , 512 k s erial eeprom: internally organi zed with 512 pa ges of 128 bytes each, the 512 k requires a 1 6 - bit data word address for random word addressing. device operation c lock and d ata t ransitions : the sda pin is normally pulled high with an external device. data on the sda pin may change only du ring scl low time periods (see figure 1 ). data changes during scl high periods will indicate a start or stop condition as defined below. s tart c ondition : a high - to - low transition of sda with scl high i s a start condition which must precede any other comman d (see figure 2 ).
ace24 la 512 a two - wire serial eeprom ver 1.1 5 s top c ondition : a low - to - high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 2 ). acknowledge : all addresses and data words are seria lly transmitted to and from the eeprom in 8 - bit words. the eeprom sends a "0" to acknowledge that it has received each word. this happens during the ninth clock cycle. s tandby mode: the ace24la512a features a low - power standby mode which is enabled: (a) u pon power - up and (b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two - wire part can be reset by following these steps: 1. clock up to 9 cycl es. 2. look for sda high in each cycle while scl is high and then. 3. create a start condition. figure 1: data validity figure 2: start and stop definition
ace24 la 512 a two - wire serial eeprom ver 1.1 6 figure 3: output acknowledge device addressing the 512 k eeprom devic es all require an 8 - bit device address word following a start condition to enable the chip for a read or write operation (see figure 4 ) the device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. thi s is common to all the serial eeprom devices. the 512 k eeprom uses a2, a1 and a0 device address bits to allow as much as eight devices on the same bus. these 3 bits must be compared to their corresponding hardwired input pins. the a2, a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation i s initiated if this bit is low. upon a compare of the device address, the eeprom will output a "0". if a compare is not made, the chip will return to a standby state. d ata s ecurity : the ace24la512a has a hardware data protection scheme that allows the user to write protect the entire memory when the wp pin is at vcc. write operations b yte w rite : a write operation requires an 8 - bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again res pond with a "0" and then clock in the first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, twr, to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 5 ).
ace24 la 512 a two - wire serial eeprom ver 1.1 7 p age w rite : a write operation requires an 8 - bi t data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a "0" and then clock in the first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, twr, to the nonvolatile memory. all inputs are disabled during this write cy cle and the eeprom will not respond until the write is complete (see figure 6 ). the data word address lower five bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the m emory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 128 data words are transmitted to the eeprom, the data word address will "roll ove r" and previous data will be overwritten. a cknowledge p olling : the identification page ( 128 bytes) is an additional page which can be written and (later) permanently locked in read - only mode. it is written by issuing the write identification page instructi on. this instruction uses the same pro tocol and format as page write (into memory array), except for the following differences: ? device type identifier = 1011b ? msb address bits b15/b 7 are don't care except for address bit b10 which must be "0". lsb address bits b5/b0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). a cknowledge p olling : once the internally time d write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the inte rnal write cycle has completed will the eeprom respond with a "0", allowing the read or write sequence to continue. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the dev ice address word is set to "1". there are three read operations: current address read, random address read and sequential read.
ace24 la 512 a two - wire serial eeprom ver 1.1 8 c urrent a ddress r ead : the internal data word address counter maintains the last address ac cessed during the last read or wri te operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. the address "roll over" during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/w rite select bit set to "1" is clocked in and acknowledged by the eeprom, the current address data word is serially clock ed out. the microcontroller does not respond with an input "0" but does generate a following stop condition (see figure 7 ). r andom r ead: a random read requires a "dummy" byte write sequence to load in the data word address. once the device address word an d data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eepr om acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a "0" but does generate a following stop condition (see figure 8 ) s equential r ead : sequential reads are initiated by either a current addres s read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data word s. when the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop c ondition (see figure 9 ). r ead i d entification p age : the identification page ( 128 bytes) is an additiona l page which can be written and (later) permanently locked in read - only mode. the identification page can be read by issuing an read identification page in struction. this instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. the msb address bits b15/b6 are don't care, the lsb address bits b5/b0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g.: when reading the identification page from location 10d, the number of bytes should be less than or equal to 118 , as the id page boundary is 128 by tes) l ock i d entification p age : the lock identification page instruction (lock id) permanently locks the identification page in read - only mode. the lock id instruction is similar to byte write (into memory array) with the following specific conditions: devi ce type identifier = 1011b address bit b10 must be ?1?; all other address bits are don't care the data byte must be equal to the binary value xxxx xx1x, where x is don't care
ace24 la 512 a two - wire serial eeprom ver 1.1 9 table 2.first word address b15 b14 b13 b12 b 11 b10 b9 b8 ta b l e 3.second word a ddress b7 b6 b5 b4 b3 b2 b1 b0 msb lsb 1 0 1 0 a2 a1 a0 r/w figure 4: device address figure 5: byte write figure 6: page write figure 7: current address read
ace24 la 512 a two - wire serial eeprom ver 1.1 10 figure 8: random read figure 9: sequential read pin capacitance applicable over recommended operating range fro m: t a = 25 , f = 1.0 mhz, v cc = +1. 7 v. symbol test condition max units conditions c i/o input / output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v
ace24 la 512 a two - wire serial eeprom ver 1.1 11 dc characteristics applicab le over recommended operating range from : t a = - 40 to +85 , v cc = +1. 7 v to +5.5v, (unless otherwise noted). symbol parameter test condition min typ max units v cc 1 supply voltage 1.7 5.5 v v cc 2 2.5 5.5 i cc1 supply current v cc =5.0v read at 400khz 0.14 0.3 ma i cc2 supply current v cc =5.0v write at 4 00 khz 0.09 0.3 ma i sb1 standby current v cc = 5.0 v v in = v cc or v ss 0.01 0.5 a i li input leakage current v in = v cc or gnd 1.0 a i lo output leakage current v out = v cc or v ss 1.0 a v il 1 input low level v cc =1.8v to 5.5v - 0. 3 v cc * 0 .3 v v ih 1 input high level v cc =1.8v to 5.5v v cc * 0.7 v cc +0. 3 v v ol 2 output low level v cc = 5.0 v i ol = 3.0 ma 0.4 v v ol 1 output low level v cc =1.7v i ol = 0.15 ma 0. 2 v
ace24 la 512 a two - wire serial eeprom ver 1.1 12 ac characteristic s applicable over recommended operating rang e from t a = - 40 to +85 , v cc = +1.7v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter 1.7v Q v cc < 2.5v 2.5v Q v cc Q 5.5v units min typ max min typ max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 0.6 0.6 s t high clock pulse width high 0.4 0.4 s t i noise suppression time 50 50 ns t aa clock low to data out valid 0.1 0.55 0.1 0.55 s t buf time the bus must be free before a new transmission can start 0.5 0.5 s t hd.sta start hold time 0 .25 0.25 s t su.sta start setup time 0.25 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in setup time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 0.3 0.3 s t su.sto stop setup time 0.25 0.25 s t dh data out hold time 50 50 ns t wr write cycle time 1.9 3 1.9 3 ms endurance 5.0 v, 25 , page mode (1) 4 m write cycles notes: 1. this parameter is characterized and is not 100% tested. 2. ac measurement conditions: rl (connects to vcc): 1.3 k inp ut pulse voltages: 0.3 vcc to 0.7 vcc input rise and fall time: 50 ns input and output timing reference voltages: 0.5 vcc the value of rl should be concerned according to the actual loading on the user's system.
ace24 la 512 a two - wire serial eeprom ver 1.1 13 figure 10 scl: seri al clock, sda: serial data i/o figure 11 scl: serial clock, sda: serial data i/o note: the write cycle time t wr is the time from a valid stop con dit ion of a write sequence to the end of the internal clear/write cycle.
ace24 la 512 a two - wire serial eeprom ver 1.1 14 packaging i nformation dip - 8 symbol min nom max note a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100bsc ea 0.300bsc 4 l 0.115 0.130 0.150 2
ace24 la 512 a two - wire serial eeprom ver 1.1 15 packaging information sop - 8 symbol min nom max a 1.35 1.75 a1 0.10 0.25 b 0.31 0.51 c 0.17 0.25 d 4.80 5.00 e1 3.81 3.99 e 5.79 6.20 e 1.27bsc l 0.40 1.27 0" 8"
ace24 la 512 a two - wire serial eeprom ver 1.1 16 packaging information tssop - 8 symbol min nom max note d 2.90 3.00 3.10 2,5 e 6.40bsc e1 4.30 4.40 4.50 3,5 a 1.20 a2 0.80 1.00 1.05 b 0.19 0.30 4 e 0.65b c l 0.45 0.60 0.75 l1 1.00ref
ace24 la 512 a two - wire serial eeprom ver 1.1 17 packaging information u son3*2 - 8 common dimension(mm) pkg ut:ultra thin ref min nom max a >0.50 0.55 0.60 a1 0.00 0.05 a3 0.15ref d 1.95 2.00 2.05 e 2.95 3.00 3.05 b 0.20 0.25 0.30 l 0.20 0.30 0.40 d2 1.25 1.40 1.50 e2 1.15 1.30 1.40 e 0.50bsc
ace24 la 512 a two - wire serial eeprom ver 1.1 18 notes ace does not assume any responsibility for use as critical components in life support devices or systems without the exp ress written approval of the president and general counsel of ace electronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and s hoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/

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